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Target Datasheet TLE7230 R/G
Smart Octal Low-Side Switch
Features Product Summary Full Protection Supply voltage VS 4.5 - 5.5 V Overload Overtemperature Drain source clamping voltage VDS(AZ)max 60 V Overvoltage On resistance RON 0.8 Low Quiescent Current< 10A 16 bit SPI (for Daisychain) Direct Parallel Control of Four Channels PWM input (demux) Parallel Inputs High or Low Active Programmable Programmable functions Boollean operation Overload behavior Power P-DSO 36 Overtemperature behavior Switching time General Fault Flag Digital Ports Compatible to 5V and 3,3 V Micro Controllers Electostatic Discharge (ESD) Protection Full reverse current capability without latchup or loss of function P-DSO-24
General description
GND
Detailed Block Diagram
PRG
VS
RESET
VS
FAULT
VDO
Octal Low-Side Switch in Smart Power Technology (SPT) with a Serial Peripheral Interface (SPI) and eight open drain DMOS output stages. The TLE 7230 R/G is protected by embedded protection functions and designed for automotive applications.
SI
VBB IN1 IN2 IN3 IN4
as Ch. 1 as Ch. 1 as Ch. 1
LOGIC
Protection Functions
Output Stage
16
OUT1
1 8
4 8
OUT8
SCLK
CS
SO
Serial Interface SPI
Output Control Buffer
GND
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Target Datasheet TLE7230 R/G
Power SO 36 package Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol GND NC NC OUT1 OUT2 IN1 IN2 VS Reset CS PRG IN3 IN4 OUT3 OUT4 NC NC GND GND NC NC OUT5 OUT6 NC VDO Fault SO SCLK SI NC NC OUT7 OUT8 NC NC GND Function Ground not connected not connected Output Channel 1 Output Channel 2 Input Channel 1 Input Channel 2 Supply Voltage Reset Chip Select Program Input Channel 3 Input Channel 4 Output Channel 3 Output Channel 4 not connected not connected Ground Ground not connected not connected Output Channel 5 Output Channel 6 not connected Supply for digital Outputs General Fault Flag Serial Data Output Serial Clock Serial Data Input not connected not connected Output Channel 7 Output Channel 8 not connected not connected Ground Pin Configuration (Top view)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
GND NC NC Out1 Out2 IN1 IN2 VS Reset CS PRG IN3 IN4 Out3 Out4 NC NC GND
GND NC NC Out8 Out7 NC NC SI SCLK SO Fault VDO NC Out6 Out5 NC NC GND
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
Power- P-DSO-36
Heat Slug internally connected to ground pins
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Target Datasheet TLE7230 R/G
SO 24 package (thermal enhanced) Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol CS IN OUT3 OUT4 GND GND GND GND OUT5 OUT6 VDO SO SCLK SI OUT7 OUT8 GND GND GND GND OUT1 OUT2 VS Reset Function Chip Select Mappable input Output Channel 3 Output Channel 4 Ground Ground Ground Ground Output Channel 5 Output Channel 6 Supply for digital Outputs Serial Data Output Serial Clock Serial Data Input Output Channel 7 Output Channel 8 Ground Ground Ground Ground Output Channel 1 Output Channel 2 Supply Voltage Reset Pin Configuration (Top view)
1 2 3 4 5 6 7 8 9 10 11 12
CS IN Out3 Out4 GND GND GND GND Out5 Out6 VDO SO
Reset Vs Out2 Out1 GND GND GND GND Out8 Out7 SI SCLK
24 23 22 21 20 19 18 17 16 15 14 13
P-DSO-24
Heat Slug internally connected to ground pins
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Maximum Ratings for Tj = - 40C to 150C
Parameter Supply Voltage Continuous Drain Source Voltage (OUT1...OUT8) Input Voltage, All Inputs and Data Lines Operating Temperature Range Storage Temperature Range Output Current per Channel (see el. characteristics) Reverse current per channel Output Clamping Energy (single pulse) ID = 0.5 A Electrostatic Discharge Voltage (Human Body Model) according to MIL STD 883D, method 3015.7 and EOS/ESD assn. standard S5.1 - 1993 Output 1-8 Pins All other Pins DIN Humidity Category, DIN 40 040 IEC Climatic Category, DIN IEC 68-1 Thermal Resistance junction - case (Power SO-36, all channels on) junction - case (SO-24, all channels on) RthJC RthJC Symbol VS VDS VIN Tj Tstg ID(lim) IR EAS Values -0.3 ... + 6 48 - 0.3 ... + 6 - 40 ... + 150 - 55 ... + 150 ID(lim)min - ID(lim)min tbd Unit V V V C A A mJ
VESD VESD
2000 2000 E 40/150/56 tbd tbd
V V
K/W
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Target Datasheet TLE7230 R/G
Electrical Characteristics
Parameter and Conditions VS = 4.5 to 5.5 V ; Tj = - 40 C to + 150 C ; Reset = H (unless otherwise specified) 1. Power Supply, Reset Supply Voltage1 Supply Current Supply Current (reset mode) Minimum Reset Duration 2. Outputs ON Resistance VS = 5 V; ID = 500 mA Output Clamping Voltage Current Limit Output Leakage Current Turn-On Time Turn-Off Time 3. Digital Inputs Input Low Voltage Input High Voltage Input Voltage Hysteresis Input Pull Down/Up Current (IN1 ... IN4) PRG, Reset Pull Up Current Input Pull Down Current (SI, SCLK) Input Pull Up Current (CS) 4. Digital Outputs (SO, Fault) SO High State Output Voltage SO Low State Output Voltage ISOH = 2 mA ISOL = 2.5 mA VSOH VSOL ISOlkg VFAULTL VVDO 0.4 --10 ---0 --0.4 10 0.4 V V A V VINL VINH VINHys IIN(1..4) IIN(PRG,Res) IIN(SI,SCLK) IIN(CS) - 0.3 2.0 --100 50 50 20 20 1.0 -V V mV A A A A VReset = L Vbb=12V ID = 0.5 A, resistive load ID = 0.5 A, resistive load TJ = 25C TJ = 150C Output OFF RDS(ON) VDS(AZ) ID(lim) ID(lkg) tON tOFF --48 1 ----0.8 --1 1.7 60 2 5 15 / 60 15 / 60 V A A s s Reset = L VS IS IS(reset) tReset,min 4.5 --10 --1 5.5 2 10 -V mA A s Symbol Values min Unit typ max
Output Tri-state Leakage Current CS = H, 0 VSO VS Fault Output Low Voltage IFAULT = 1.6 mA
1
For VS < 4.5V the power stages are switched according the input signals and data bits or are definitely switched off. Page 5 12. Oct. 2003
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Target Datasheet TLE7230 R/G
Electrical Characteristics cont.
Parameter and Conditions VS = 4.5 to 5.5 V ; Tj = - 40 C to + 150 C ; Reset = H (unless otherwise specified) 5. Diagnostic Functions Open Load Detection Voltage Output Pull Down Current Fault Delay Time Overload switch off delay time Short to Ground Detection Voltage Short to Ground Detection Current Overload Threshold Current Overtemperature Shutdown Threshold Hysteresis2
2
Symbol
Values min typ max
Unit
VDS(OL) IPD(OL) td(fault) Td(off) VDS(SHG) ISHG ID(lim) 1...8 Tth(sd) Thys 1 175 -10
VS -2 90 100 50 VS -2.9 -100 2 -10 200 --
V A s s V A A C K
6. SPI-Timing (for VVDO = 4.5V to 5.5V) Serial Clock Frequency (depending on SO load) Serial Clock Period (1/fclk) Serial Clock High Time Serial Clock Low Time
fSCK
DC 200 50 50 250 250 20 20 -tbd ----
-----------tbd tbd tbd
5 -------150 --
MHz ns ns ns ns ns ns ns ns ns ns
tp(SCK) tSCKH tSCKL
Enable Lead Time (falling edge of CS to rising edge of CLK) tlead Enable Lag Time (falling edge of CLK to rising edge ofCS) Data Setup Time (required time SI to falling of CLK) Data Hold Time (falling edge of CLK to SI) Disable Time @ CL = 50 pF
3 2
tlag tSU tH tDIS tdt
Transfer Delay Time (CS high time between two accesses) Data Valid Time CL = 50 pF2 CL = 100 pF2 CL = 220 pF2
tvalid
2 3
This parameter is not subject to production test This time is necessary between two write accesses. To get the correct diagnostic information, the transfer delay time has to be extended to the maximum fault delay time td(fault)max = 200s. Page 6 12. Oct. 2003
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Target Datasheet TLE7230 R/G
Functional Description
The TLE 7230 R/G is an octal-low-side power switch which provides a serial peripheral interface (SPI) to control the 8 power DMOS switches, as well as diagnostic feedback. The power transistors are protected4) against overload (current limitation), overtemperature and against overvoltage by an active zener clamp. The diagnostic logic recognizes a fault condition which can be read out via the serial diagnostic output (SO). Output Stage Control: Parallel Control or SPI Control The Output stages can be controlled by parallel Inputs or by SPI command. The IC can be programmed (by SPI) to switch the outputs according to the corresponding SPI command bit or to a combination of SPI bit and parallel input signal. The logic combination of parallel and serial signal is programmable by SPI (Boolean operation) to logic "AND" or "OR" The respective SPI databits are high active, the parallel Inputs are high or low active according to the PRG pin (see pin description). Boolean operation: The logic combination of the parallel and the serial input signal can be configured by an SPI command for each of the 8 channels individually. Logic "AND" or logic "OR" is possible. parallel in off off on on serial in off on off on Output "OR" off on on on Output "AND" off off off on
Mappable parallel input (IN 4): By SPI Command the parallel input 4 (IN4 or IN) can be defined as parallel input for one or more power outputs. Depending on the Input Map Register this input can be used to controll one up to eight of the parallel outputs. Default operation: IN4 / IN is the parallel input for channel 4.
Input Map register Input buffer IN n (1..3) Input buffer IN 4 Boolean register
Boolean register Input buffer IN 4
& 1
Output Latch
&
Output Latch
1
serial controll register Channel 4 to 8 Input Map register
serial controll register Channel 1 to 3
Signal logic channel 1 to 3
Signal logic channel 4 to 8
Switching speed / Slew rate: The switching speed / slew rate of all 8 channels can be configured by SPI for slow or fast switching speed (1:5) for each channel individually. Overtemperature Behavior: Each channel has an overtemperature sensor and is individually protected against overtemperature. As soon as overtemperature occurs the channel is immediately turned off and the overtmperature information is reported by diagnosis. In this case there are two different behaviours of the affected channel that can be selected by SPI (for all channels individually). Autorestart: as long as the input signal of the channel remains on (e.g. parallel input high) the channel turns automatically on again after cooling down.
4
)The integrated protection functions prevent an IC destruction under fault conditions and may not be used in normal operation or permanently. Page 7 12. Oct. 2003
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Target Datasheet TLE7230 R/G
Latching: After overtemperature shutdown the channel stays off until the overtemperature latch is reset by a new L H transition of the input signal. Note: The overtemperature sensors of the output channels are only active if the channel is turned on. Low Quiescent current mode (Sleep mode) : By applying ay low signal at the Reset Pin the device can be set to Sleep mode. In this mode all outputs are turned off, the diagnosis and biasing is disabled, the diagnosis and the on/off register are reseted and the current consumption drastically reduced (<10A). After a reset the outputs are Off, except the outputs are controlled by parallel inputs. Overload Protection: The IC can be programmed to react in different ways to overload. Only Current limit: The IC actively limits the current to the specified current lmit value. If the current limitation is active for longer than the fault filtering time this fault is reported and stored in the Fault register. The channel is not shutdown. Current limit + shutdown: The IC actively limits the current to the specified current lmit value. If this current limit is active for more than the specified Overload switch off delay time the affected channel is turned off and the fault is reported and stored in the fault register. To turn on the channel again this overload latch has to be reset before with an L H transition of the input signal (parallel /SPI depending on the programmed operation).
Pin description:
OUTPUT 1 to 8 - Drain pins of the 8 channels. Output pins and connected to the load. GND - Ground pins. IN 1 to 3 - Parallel Input Pins of the channels 1 to 3 IN 4 / IN - Mappable parallel Input Pin. Can be assigned to different outputs by SPI command. Default Output is OUT4
PRG - Program pin.
PRG = High (VS): Parallel inputs 1 to 4 are high active PRG = Low (GND): Parallel inputs 1 to 4 are low active. If the parallel input pins are not connected (independent of high or low activity) it is guaranteed that the channels 1 to 4 are switched OFF. PRG pin itself is internally pulled up when it is not connected. Reset - If the reset pin is in a logic low state, it clears the SPI shift register and switches all outputs OFF. An internal pull-up structure is provided on chip. Fault - There is a general fault pin (open drain) which shows a high to low transition as soon as an error occurs for any one of the eight channels. This fault indication can be used to generate a C interrupt. Therefore a `diagnosis' interrupt routine need only be called after this fault indication. This saves processor time compared to a cyclic reading of the SO information.
VDO - Supply pin of the push-pull digital output drivers. This pin can be used to vary the high-state output voltage of the SO pin. Vs - Logic supply pin. This pin is used to supply the integrated circuitry. CS - Chip Select of the SPI
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Target Datasheet TLE7230 R/G
SO - Signal Output of the Serial Peripheral Interface SI - Signal Input of the Serial Peripheral Interface. The pin has an internal pull down structure. SCLK - Clock Input of the Serial Peripheral Interface. The pin has an internal pull down structure
SPI
The SPI is a Serial Peripheral Interface with 4 digital pins and an 16 bit shift register. The SPI is used to configure and program the device, turn on and off channels and to read detailed diagnostic information.
CS SCLK SI SO
SPI
SPI Signal Description:
CS - Chip Select. The system microcontroller selects the TLE 7230 R/G by means of the CS pin. Whenever the pin is in a logic low state, data can be transferred from the C and vice versa.
LSB MSB
internal logic registers
CS SI SO
CS = H : Any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state.
CS = H L : * diagnostic information is transferred 16 bit SPI shift register Serial input Serial output from the diagnosis register into the SPI (diagnosis) data MSB first CS shift register. (in sleep mode no tranfer MSB first of diagnostic information) diagnosis register * serial input data can be clocked into the LSB MSB SPI shift register from then on * SO changes from high impedance state to logic high or low state corresponding to the SO bits CS = L : SPI is working like a shift register. With each clock signal at the SCLK pin the state of the SI is read into the SPI shift-register (falling clock edge) and one diagnosis bit is written out of SO (rising rising edge). CS = L H: * transfer of SI bits from SPI shift register into the internal logic registers * reset of diagnosis register if sent command was valid To avoid any false clocking the serial clock input pin SCLK should be logic low state during high to low transition of CS. The SPI of the TLE7230G/R has a modulo 8 counter integrated. If the number of clock signals is not an integer multiple of 8 the SPI will not accept the data in the shift register and the fault register will not be reset. SCLK - Serial Clock. The serial clock pin clocks the internal SPI shift register of the TLE7230G/R. The serial input (SI) accepts data into the input SPI shift register on the falling edge if while the serial output (SO) shifts diagnostic information out of the SPI shift register on the rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever chip select CS makes any transition. SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit (MSB) first. SI information is read in on the falling edge . Input data is latched in the SPI shift register and then transferred to the internal registers of the logic.
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Target Datasheet TLE7230 R/G
The input data consist of 16 bit, made up of x control bits and y data bits. The control word is used to program the device, to operate it in a certain mode as well as providing diagnostic information (see SPI Commands). SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant bit (MSB) first. SO is in a high impedance state until the CS pin goes to a logic low state. New diagnostic data will appear at the SO pin following the rising edge.
SPI Control and Commands:
MSB SI: SO: SO: 14 13 x 12 x 11 x Ch 6 10 9 ADDR Ch 5 Ch 4 Ch 3 DATA 8 7 6 5 4 3 2 1 LSB
CMD
DATA Ch 2 Ch 1
SO standard diagnosis Ch 8 Ch 7
SO after read command in previous frame 0 1 0 0 0 ADDR
CMD
Command : 0 0 : Diagnosis Only : Reads out the diagnosis register. This command has no other influence on the device. 0 1 : Read register : With the next SO dataframe the content of the addressed register will be sent. 1 0 : Reset Registers Sets back all internal registers. Logic registers to default and Fault registers to no error. 1 1 : Write register : The data of the SI word will be written to the addressed register. No valid Commands : If the first 8 bit of the SI word contain no valid bit combination it will not lead to an reaction (register value change, switching channels, ...) of the IC. After Chip Select giong L H the diagnosis register will not be reset.
ADDR DATA Ch x
Address : Pointer to register for read and write command Data: Data written to or read from register selected by address ADDR Standard diagnosis for channel x: Details see "SPI Diagnostics"
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Register Description:
Name MAP BOL OVL OVT SLE STA CTL Nr. 1 2 3 4 5 6 7 7 Ch8 Ch8 Ch8 Ch8 Ch8 OUT8 Ch8 6 Ch7 Ch7 Ch7 Ch7 Ch7 OUT7 Ch7 5 Ch6 Ch6 Ch6 Ch6 Ch6 OUT6 Ch6 4 Ch5 Ch5 Ch5 Ch5 Ch5 OUT5 Ch5 3 Ch4 Ch4 Ch4 Ch4 Ch4 OUT4 Ch4 2 Ch3 Ch3 Ch3 Ch3 Ch3 OUT3 Ch3 1 Ch2 Ch2 Ch2 Ch2 Ch2 OUT2 Ch2 0 Ch1 Ch1 Ch1 Ch1 Ch1 OUT1 Ch1 ADDR 001 010 011 100 101 110 111 default 08H 00H 00H 00H 00H 00H 00H
Input Mapping Rgister (MAP) Defined to which outputs the IN4 / IN is assigned (can be one up to all) 0.. No connection to IN4 / IN 1.. Output can be controlled with IN4 / IN pin Boolean operation Register (BOL) The logic operation for serial and parallel control signal is defined for all channels individually 0.. Logic "OR" 1.. Logic "AND" Overload Behavior Rgister (OVL) The overload behavior of a single channel is defined. 0.. Current limit without shutdown of the channel 1.. Current limit with latching overload shutdown of the channel Overtemperature Behavior Register (OVT) The overtemperature behavior of a single channel is defined. 0.. Autorestart after cooling down 1.. Latching shutdown on overtemperature Switching Speed / Slew Rate Register (SLE) The switching speed of the channels is defined 0.. fast (10s) 1.. slow (50s) Output State Register (STA) Reads back the state of the output (read only register) 0: DMOS off 1: DMOS on Serial Output Control Register (CTL) Sets the serial controll bits for switching the output stages. 0: Output off 1: Output on
SPI Diagnostics:
As soon as a fault occurs for longer than the fault filtering time, the fault information is latched into the diagnosis register (and the Fault pin will change from high to low state). A new error on the same channel will over-write the old error report. Serial data out pin (SO) is in a high impedance state when CS is high. If CS receives a LOW signal, all diagnosis bits can be shifted out serially. If the sent comV1.1 Page 11 12. Oct. 2003
Target Datasheet TLE7230 R/G
mand was valid the rising edge of CS will reset all diagnosis registers and restart the fault filtering time. In case of an invalid command the device will ignore the data bits and the diagnosis register will not be reset at the rising CS edge. Figure 1: Two bits per channel diagnostic feedback
Diagnostic Serial Data O ut SO
M SB 15 3 2 1 LSB 0
C h.8
C h.2
C h.1
HH HL LH LL
N orm al function O verload , Shorted Load or O verte m perature O pen Load (off) Short to G N D
For Full Diagnosis there are two diagnostic bits per channel configured as shown in Figure 1. Normal function: The bit combination HH indicates that there is no fault condition, i.e. normal function. Overload, Shorted Load or Overtemperature: HL is set when the current limitation gets active, i.e. there is a overload, short to supply or overtemperature condition. The second reason for this bit combination is overtemperature of the corresponding channel. Open load: LH is set when open load is detected (in off state of the channel) Short to GND : LL is set when this condition is detected (in off state)
Timing Figures
Figure 5: Power Outputs
VIN
t
VDS 80% 20%
tON
tOFF
t
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Target Datasheet TLE7230 R/G
Figure 6: Serial Interface Timing Diagram
CS
0.7VS
0.2 VS tSCKH tlag
0.7VS 0.2VS
tdt
SCLK
tlead tSCKL tH
0.7VS 0.2VS
tSU
SI
Figure 7: Input Timing Diagram SO Valid Time Waveforms
0.7 V S
Enable and Disable Time Waveforms
CS
0.2 V S
SCLK t valid
t D is SO SO
0.7 V S 0.2 V S 0.7 V S 0.2 V S
SO
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(all dimensions in mm)
P-DSO 36-12
TLE 7230 R
Ordering Code
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P-DSO 24
TLE 7230 G Ordering Code
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Target Datasheet TLE7230 R/G
Published by Infineon Technologies AG, Bereichs Kommunikation St.-Martin-Strasse 76, D-81541 Munchen (c) Infineon Technologies AG 1999 All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer.
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For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
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